A synchronous Gigabit Ethernet protocol stack for high-throughput UDP/IP applications

摘要

State of the art detector readout electronics require high-throughput dataacquisition (DAQ) systems. In many applications, e. g. for medical imaging, thefront-end electronics are set up as separate modules in a distributed DAQ. Astandardized interface between the modules and a central data unit isessential. The requirements on such an interface are varied, but demand almostalways a high throughput of data. Beyond this challenge, a Gigabit Ethernetinterface is predestined for the broad requirements of Systems-on-a-Chip (SoC)up to large-scale DAQ systems. We have implemented an embedded protocol stackfor a Field Programmable Gate Array (FPGA) capable of high-throughput datatransmission and clock synchronization. A versatile stack architecture for theUser Datagram Protocol (UDP) and Internet Control Message Protocol (ICMP) overInternet Protocol (IP) such as Address Resolution Protocol (ARP) as well asPrecision Time Protocol (PTP) is presented. With a point-to-point connection toa host in a MicroTCA system we achieved the theoretical maximum data throughputlimited by UDP both for 1000BASE-T and 1000BASE-KX links. Furthermore, we showthat the random jitter of a synchronous clock over a 1000BASE-T link for a PTPapplication is below 60 ps.